B69000-电脑主板芯片

In-Circuit TestModeAnalysis for theHiQVPro™ControllerApplication NoteRevision

1.0June1998PRELIMINARYCopyright NoticeCopyright©1998Chips and Technologies,Inc.,a subsidiaryof Intel Corporation,ALLRIGHTS RESERVED.This manualis copyrightedby Chips andTechnologies,Inc.,a subsidiaryof IntelCorporation.You maynot reproduce,transmit,transcribe,store ina retrievalsystem,or translateinto anylanguageor computerlanguage,in anyform orby anymeans-electronic,mechanical,magnetic,optical,chemical,manual,or otherwise-any partof thispublication withoutthe expresswrittenpermission ofChips andTechnologies,Inc.,a subsidiaryof IntelCorporation.Restricted RightsLegendUse,duplication,or disclosureby theGovernment issubject torestrictions setforth insubparagraphc liiof theRights inTechnical Dataand ComputerSoftware clauseat

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7013.Trademark AcknowledgmentCHIPSLogo is a registeredtrademark ofChips andTechnologies,Inc.,a subsidiaryof IntelCorporation.HiQVideo,isatrademark ofChips andTechnologies,Inc.,a subsidiaryof IntelCorporation.All othertrademarks arethe propertyof theirrespective holders.DisclaimerThis documentprovides generalinformation for the customer.Chips andTechnologies,Inc.,asubsidiary of IntelCorporation,reserves theright tomodify the information containedherein asnecessaryand thecustomer shouldensure thatit hasthe mostrecent revisionof thedocument.CHIPS makesno warrantyfor theuse ofits productsand bearsno responsibilityfor anyerrors whichmayappear in this document.The customershould beon noticethat manydifferent partiesholdpatents onproducts,components,and processeswithin thepersonal computerindustry.Customersshould ensurethat theiruse of the productsdoes notinfringe uponany patents.CHIPS respectsthepatent rightsof thirdparties andshall notparticipate indirect orindirect patentinfringement.Revision HistoryRevision DateBy Comment

0.15/21/98DJ/lnc InitialRelease.

1.05/29/98DJ/lnc Formattingfor useability.Table ofContents

1.1Introduction

1.06/5/9869000Users Guide1In-Circuit TestMode Analysisforthe HiQVideo™Series Controllers

1.OlntroductionThe In-Circuit TestICTModefortheHiQVideo Seriesof graphicscontrollers isa statewhereall digitalpins except RCLK,STNDBY#and thepower and ground pinsmay betested individuallytodetermine ifthey areproperly connected.This applicationnote providesthe detailson howthecontroller worksinthismode.

2.0OperationIPull allpins highexceptRCLK,STNDBY#and powerandgroundpins.2Pull RESETand RMD4low.3Toggle theRCLK pintwice tohigh.This willstart thetest modeas shownin Figure1,line A.Stoppulsing afterthe secondpulse.4Pull RESETand RMD4high.When theRESET goeslow again,you areready totest theindividualpinssee lineB in Figure

1.5Toggle the pins lowone ata timestarting withCFGO DI8as showninFigure1,lines C,Dand Ein the ordergiven inTable

1.The VSYNCpin willtoggle witheach pintested.6If VSYNCfails totoggle whenany pinis pulledlow,thepinis notconnected oris somehowdefective.For properoperation ofthein-circuit testand asa safetyprecaution,everything noton thering-down listTable1should bepulled high.+,36@69000In-Circuit TestingSubject toChange WithoutNotice Revision

1.06/5/98269000Users Guide+,36@69000In-Circuit TestingSubject toChange WithoutNoticeRevision

1.06/5/98Figure1:Timing Diagramfor ICTModelowRCLK RESET#o oooVSYNCAB RMD4TM DIsee listCFGOhighhighC CFGHowD highCFG21owE69000Users Guide3VDDRES ETCFGORM A17VSYNCFigure2:NANDGateChain forthe69000+,36®69000In-Circuit TestingSubject toChange WithoutNotice Revision

1.06/5/98469000Users GuideABCDEFGHJKLMNPRTUVWY20CFG4CFG2N/C N/C N/C N/C N/C N/C N/C N/C RMA17N/C N/C N/C N/C N/CVP1VP6VP10RSVD2019CFG6CFG5CFG1N/C N/C N/C N/C N/C N/C N/C RMA16N/C N/CN/C N/C VP2VP5VP9VP11VP141918N/C CFG7CFG3CFG0N/C N/C N/C N/C N/C N/C N/CN/C N/C N/C VP0VP4VP8VP13VP15VCLK1817RMA2N/C CFG8TMD0N/C N/C MEMGNDMEMVCC N/C N/C N/C N/C MEMVCCMEMGND VP3VP7VP12PCLK HREFP331716RMA4RMA1N/C CFG9GPIO4VREF P34P311615RMA7RMA5RMA3RMA0P35P32P30P281514RMA10RMA8RMA6MEMGND GNDP29P27P251413RMA14RMA11RMA9MEMVCC TOVCCP26P24P211312TMD1RM A15RMA13RMA1212GND GND GND RGNDP23P22CORVCC P201211N/C N/C N/CN/C11GND GND GND RGNDP16P19P18P171110N/CCFG1OCFG11N/C1OGND GNDGND RGNDP15P12P13P14109CFG12CFG13CFG15CORVCC9GNDGNDGND RGNDP7P8P10P1198CFG14RMD0RMD2RS VDJKLM IOVCCP4P6P987RMD1RMD3RMD5GNDGNDP1P3P576RMD4RMD6ROMOE#GPIO7ENABKL MP0P265RMD7RSVD RSVDDCKVCC DACVCCENAVDDFLM SHFCLK54TNT#DCKGND DCKVCCRSVD STNDBYAD30GND IOVCCAD20TRDY#DEVSEL AD13IOVCC GNDAD2GPIO1DDC CLKGRN ENA VEE LP43DCKGND MCKVCCREFCLK RSVDAD31AD27AD24AD23AD19C/BE2#SERR#AD14AD10C/BE0#AD5AD1HSYNC DDCDATA BLUERED32MCKGND DCLKINRSVDBUSCLK AD29AD25TDSEL AD21AD17FR AME#PERR#C/BE1AD12AD9AD7AD3ADOVS YNCRSET DACGND21RSVD MCLKINRESET#AD28AD26C/BE#AD22AD18AD16IRDY#STOP#PAR AD15AD11AD8AD6AD4GPIOOIOVCC RGND1ABCDEFGHJKLMNPRTUVWYFigure3:BGA PinDiagramfor69000Top View+,36@69000In-Circuit TestingSubject toChange WithoutNotice Revision

1.06/5/9869000Users Guide5Table1:The sequenceoftheNAND gatechain.Seq NameBallSeq NameBallSeq NameBallSeq NameBall1RESET#CI41BCLKD281AD5R3121P23UI22CFG0D1842AD31E382AD4U1122P24W133CFG1C1943AD30F483AD3T2123P25Y144CGF2B2044AD29E284AD2R4124P26V135CFG3C1845AD28DI85ADI T3125P27W146CFG4A2046AD27F386AD0U2126P28Y157CFG5B1947AD26E187GPIO0T4127P29V148CFG6A1948AD25F288GPIO1H2128P30W159CFG7B1849AD24G389GPIO2V3129P31Y1610CFG8C1750BE3F190GPIO3U4130P32V1511CFG9D1651IDSEL G291ENAVEEW4131P33Y1712RMA0D1552AD23H392ENAVDD V5132P34W1613RMA1B1653AD22G193ENABKL U6133P35U1514RMA2A1754AD21H294FLM W5134VREF V1615RMA3C1555AD20J495LPY4135HREF W1716RMA4A1656AD19J396M V6136VCLK Y1817RMA5B1557AD18H197SHFCLK Y5137GPIO4U1618RMA6C1458AD17J298P0W6138PCLK V1719RMA7A1559AD16J199P1V7139VP15W1820RMA8B1460BE2K3100P2Y6140VP14Y1921RMA9Cl36IFRAME#K2101P3W7141VP13V1822RMA10A1462IRDY#K1102P4V8142VP12U1723RMA11B1363TRDY#K4103P5Y7143VP11W1924RMA12D1264DEVSEL#L4104P6W8144VP10W2025RMA13/CFG11C12/C1065STOP L1105P7U9145VP9V1926RMA14/CFG12A13/A966PERR#L2106P8V9146VP8U1827RMA15/CFG10B12/B1067SERR#L3107P9Y8147VP7T1728GPIO5N18*68PARITY M1108P10W9148VP6V2029GPIO7P2069BE1M2109P11Y9149VP5UI930RMD0/CFG13B8/B970AD15N1110P12V10150VP4T1831RMD1/CFG12A7/A871AD14M3111P13W10151VP3R1732RMD2/CFG15C8/C972AD13M4112P14Y10152VP2T1933RMD3/TM0B7/D1773AD12N2113P15U10153VP1U2034RMD4/TM1A6/A1274AD11P1114P16U11154VP0R1835RMD5C775AD10N3115P17Y11155RMA16L1936RMD6B676AD9P2116P18W11156RMA17L2037RMD7A577AD8R1117P19V11157HSYNC U338ROMOE#C678BE0P3118P20Y12158VSYNC V239TMD0D1779AD7R2119P21Y1315940INT#A480AD6T1120P22V12160*GPIO5ball N18is listedas NCinthepin diagram.It mustbe connectedforthein-circuittest towork properly.+,36@69000In-Circuit TestingSubject toChange WithoutNotice Revision

1.0ChipsandTechnologies,Inc.a subsidiaryofIntelCorporation Title:69000ICT2950Zanker RoadPublicationNo.:AN120San Jose,California95134Stock No.:020120-000Phone:408-434-0600RevisionNo.:

1.0FAX:408-894-2077Date:6/05/98。